Minimizing the E ect of Clock Skew Via Circuit
نویسندگان
چکیده
Clock skew is often cited as an impediment to designing high-performance synchronous circuits. Clock skew reduces the performance of a circuit by reducing the time available for computation, and it may even cause circuit failure by allowing race conditions. In this paper, we show how to use retiming to reduce the e ect of clock skew in both edge-clocked and level-clocked circuits. We include both xed clock skew, for example skew which results from clock distribution wiring and bu ering, and variable clock skew which results from uncontrolled variation in process parameter and operating conditions. By including xed skew in the maximum constraint equations retiming can nd the fastest circuit given that skew. By including variable skew, retiming can also generate the circuit that tolerates the most variation in clock skew for a given clock frequency. Clock skew can also be used to speed up circuits using a technique similar to retiming described by Fishburn [2]. We describe a method for combining this technique which uses added clock skew with retiming to optimize the performance of edge-clocked circuits.
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